JEDEC JESD82-6A
JEDEC JESD82-6A 2004-NOV-01 Defnton of the SSTV32852 25-V 24-Bt to 48-Bt SSTL_2 Regstered Buffer for 1U Stacked DDR DMM Applcatons
JEDEC JESD82-6A 2004-NOV-01 Defnton of the SSTV32852 25-V 24-Bt to 48-Bt SSTL_2 Regstered Buffer for 1U Stacked DDR DMM Applcatons
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.