JEDEC JESD8-6
JEDEC JESD8-6 1995-JAN-01 Hgh Speed Transcever Logc HSTL A 15V Output Buffer Supply Voltage Based nterface Standard for Dgtal ntegrated Crcuts
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This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz.